Modulating method and demodulating apparatus

ABSTRACT

A modulation apparatus for converting digital data having the basic data length equal to m bits into a variable length code (d, k; m, n; r) having the basic codeword length of n bits is disclosed. The apparatus includes an encoder 12 for determining the constraint length i of data supplied from a shift register 11, based upon m bits as a unit, a selector 13, plural conversion tables 14 1  and an unfixed bit processing circuit 16 1 . The selector 13 selects one of the conversion tables 14 1  based upon the constraint length i and transmits m×i bit data to the selected conversion table 14 1 , which then converts the m×i bit data into n×i bit codewords. The unfixed bit processing circuit 16 1  sets a bit at a preset position of a codeword among the codewords which gives an infinite value of the maximum run, or a bit at a preset position of a codeword among the codewords which has the maximum number of consecutive &#34;0&#34;s from the least significant bit towards upper order side bits, as being an unfixed bit, and sets the unfixed bit to &#34;1&#34; if d or more &#34;0&#34;s are consecutive to the unfixed bit. With the present modulation apparatus, the minimum length between transitions T min  may be enlarged as compared to that in EFM for increasing the recording density, while the maximum length of transitions T max  may also be increased as compared to that for VFM.

BACKGROUND OF THE INVENTION

This invention relates to a modulating method and a demodulatingapparatus and, more particularly, to a modulating method for modulatingdata so as to be suited to transmission or recording of data on arecording medium and a demodulation apparatus for reproducing the databy demodulating the modulated coded data resulting from thedemodulation.

When transmitting the data or recording the data on the recordingmedium, such as a magneto-optical disc or an optical disc, the data aremodulated so as to be suited for transmission or recording. Block codinghas been known as one of such modulating techniques. The block codingconsists of blocking an input data string into units (data words) eachconsisting of m×1 bits and translating the data words into codewords,each consisting of n×1 bits, in accordance with an appropriate codingrule. The block coding becomes a fixed length code if i=1 and becomes avariable length code if i may assume multiple values, that is if i>1,with the maximum value of i being i_(max) =r). The code produced byblock coding is termed the variable length code (d, k; m, n; r), where iis termed a constraint length, with i_(max) being equal to the maximumconstraint length r, d is the minimum number of the same consecutivesymbols, that is a so-called minimum run of O's, and k is the maximumnumber of the same consecutive symbols, that is a so-called maximum runof O's.

When recording the variable length code on, for example, an opticaldisc, it is modulated into so-called non-return to zero code (NRZ code)and recorded based upon the NRZ modulated variable length code, referredto hereinafter as the recording waveform data string. With the minimumlength between transitions and the maximum length between transitions ofthe recording waveform data string being T_(min) and T_(max),respectively, it is desirable from the viewpoint of the recordingdensity that the minimum length between transitions T_(min) be long,that is that the minimum run d be large, while it is desirable from theviewpoint of clock reproduction and jitter that the maximum lengthbetween transitions T_(max) be short, that is that the maximum run k besmall. A variety of modulation methods have been proposed with which theabove conditions are met.

In the case of an optical disc having audio data recorded thereon, thatis a so-called compact disc (CD), a so-called eight-to-fourteenmodulation (EFM) is employed. This modulation method is a variablelength code (2, 10; 8, 17; 1) in which, if the interval between bits(bit length) of the recording waveform data string is T, the minimumlength, between transitions T_(min) is (2+1)T or 3T. If the intervalbetween bits of the data string is T1, the minimum length betweentransitions T_(1min) is ((8/17)×3)T₁ or 1.41T₁. In the followingdescription, the indication of the bit length T is directly followed bythe bracketed indication of the corresponding bit length T₁. The maximumlength between transitions T_(max) (T_(1max)) is 11T (5.18T₁,), whilethe window margin T_(W), which stands for the allowable jitter, isrepresented as (m/n)×T, and has a value equal to (8/17)T or 0.47T. Withsuch a CD, it may be contemplated to diminish the minimum pit lengthcorresponding to the minimum length between transitions T_(min)(T_(1max)) on the optical disc. However, if the minimum pit lengthbecomes excessively shorter than the spot size of the laser beam, itbecomes difficult to detect the pits so that errors tend to be produced.On the other hand, limitations are imposed on increasing the recordingdensity by diminishing the wavelength of the laser light source fordiminishing the spot size.

With the above in view, there has also been developed a modulationmethod whereby the minimum pit length on the optical disc, that is theminimum length between transitions T_(min) (T_(1min)), may be increasedwithout diminishing the information volume.

For example, as shown in table 1, there has also been proposed avariable length code (4, 22; 2, 5; 5) in which the minimum lengthbetween transitions T_(min) is increased to 5T (2T₁) for increasing therecording density as compared to EFM. This modulation method is referredto hereinafter as variable five modulation (VFM). With the VFM, themaximum length between transitions T_(max) (T_(1max)) increased to 23T(9.2T₁,) as compared to the maximum length between transitions T_(max)(T_(1max)) of EFM which is equal to 11T (5.18T₁,). That is, the VFM isnot advantageous from the viewpoint of clock reproduction and jitter andrenders the designing of the apparatus difficult.

                  TABLE 1a                                                        ______________________________________                                        data words          code words                                                ______________________________________                                        i=1    11           00000                                                            10           10000                                                            111111       00001 00001 00000                                         ii=2   0111         01000 00000                                                      0110         00100 00000                                                      0101         00010 00000                                                      0100         00001 00000                                               i=3    001111       01000 01000 00000                                                001110       01000 00100 00000                                                001101       01000 00010 00000                                                001100       01000 00001 00000                                                001011       00010 00001 00000                                                001010       00100 00100 00000                                                001001       00100 00010 00000                                                001000       00100 00001 00000                                                000111       00010 00010 00000                                         i=4    00011011     01000 01000 01000 00000                                          00011010     01000 01000 00100 00000                                          00011001     01000 01000 00010 00000                                          00011000     01000 01000 00001 00000                                          00010111     01000 00010 00001 00000                                          00010110     01000 00100 00100 00000                                          00010101     01000 00100 00010 00000                                          00010100     01000 00100 00001 00000                                          00010011     01000 00010 00010 00000                                          00010010     00100 00100 00100 00000                                          00010001     00100 00100 00010 00000                                          00010000     00100 00100 00001 00000                                          00001111     00010 00001 00001 00000                                          00001110     00100 00001 00001 00000                                          00001101     00100 00010 00010 00000                                          00001100     00100 00010 00001 00000                                          00001011     01000 00001 00001 00000                                          00001010     00001 00001 00001 00000                                          00001001     00010 00010 00010 00000                                          00001000     00010 00010 00001 00000                                   ______________________________________                                    

                  TABLE 1b                                                        ______________________________________                                        data words          code words                                                ______________________________________                                        i=5    0000011111   01000 01000 01000 01000 00000                                    0000011110   01000 01000 01000 00100 00000                                    0000011101   01000 01000 01000 00010 00000                                    0000011100   01000 01000 01000 00001 00000                                    0000011011   01000 01000 00010 00001 00000                                    0000011010   01000 01000 00100 00100 00000                                    0000011001   01000 01000 00100 00010 00000                                    0000011000   01000 01000 00100 00001 00000                                    0000010111   01000 01000 00010 00010 00000                                    0000010110   01000 00100 00100 00100 00000                                    0000010101   01000 00100 00100 00010 00000                                    0000010100   01000 00100 00100 00001 00000                                    0000010011   01000 00010 00001 00001 00000                                    0000010010   01000 00100 00001 00001 00000                                    0000010001   01000 00100 00010 00010 00000                                    0000010100   01000 00100 00010 00001 00000                                    0000001111   01000 01000 00001 00001 00000                                    0000001110   01000 00001 00001 00001 00000                                    0000001101   01000 00010 00010 00010 00000                                    0000001100   01000 00010 00010 00001 00000                                    0000001011   00100 00100 00010 00010 00000                                    0000001010   00100 00100 00100 00100 00100                                    0000001001   00100 00100 00100 00010 00000                                    0000001000   00100 00100 00100 00001 00000                                    0000000111   00100 00100 00010 00001 00000                                    0000000110   00100 00100 00001 00001 00100                                    0000000101   00100 00010 00010 00010 00000                                    0000000100   00100 00010 00010 00001 00000                                    0000000011   00100 00100 00010 00001 00000                                    0000000010   00100 00100 00001 00001 00000                                    0000000001   00100 00010 00010 00010 00000                                    0000000000   00100 00010 00010 00001 00000                                                 00010 00001 00001 00001 00000                                                 00001 00001 00001 00001 00000                                                 SYNC for mod2to4d5                                                      ASYNC    23T 21T 6T                                                           BSYNC    21T 23T 6T                                             ______________________________________                                    

In other words, although it is necessary to increase the minimum lengthbetween transitions T_(min) for increasing the recording density, it isnecessary to reduce the maximum length between transitions T_(max)simultaneously to as small a value as possible in order to assure theoperating reliability of the apparatus. That is, a smaller value of theratio of the maximum length between transitions to the minimum lengthbetween transitions is desirable. Specifically, the ratio T_(max)/T_(min) =11T/3T=3.67 for EFM, while the same ratio for VFM is23T/5T=4.60.

In sum, while it is necessary to increase the minimum length betweentransitions T_(min) (T_(1min)), that is the minimum run d, of thevariable length code produced on modulation in order to increase therecording density for a recording medium, such as an optical disc, themaximum length between transitions T_(max) (T_(1max)), that is themaximum run k, is undesirably increased with the conventional modulationmethods.

SUMMARY OF THE INVENTION

In view of the above-described status of the art, it is a principalobject of the present invention to provide a modulation method wherebythe minimum run d may be enlarged as compared to that of EFM to assurehigh density recording, and the maximum run k may be diminished ascompared to that of VFM, and a demodulating apparatus whereby thevariable length code resulting from such modulation may be demodulatedin order to reproduce the data.

According to a first modulation method of the present invention, datahaving a minimum run of 4 or more and a basic data length of m bits isconverted into a variable length code (d, k; m, n; r) having a basiccode length of n bits, which has a bit at a preset position of acodeword which has the possibility of giving an infinite number (∞) forthe maximum run k and a bit at a preset position of a codeword whichgives the maximum number of "0"s consecutive from the LSB towards upperorder bit side of the codeword is set as being an unfixed bit.

According to a second modulation method of the present invention, theunfixed bit as defined in the first modulation method is set to "1" whend or more bits are consecutive to the unfixed bit.

A modulation apparatus according to the present invention inverselyconverts the variable length code (d, k; m, n; r) having the minimum rund equal to 4 or more and the basic codeword length of n bits, andincluding an unfixed codeword having an unfixed bit at a preset positionthe value of which is determined by the number of "0"s consecutive tosuch bit, and includes detecting the codeword having the unfixed bit,means for determining the constraint length of the variable codedepending on the results of detection by the unfixed codeword detectionmeans, and inverse conversion means for inverse converting the variablelength code into data based on the constraint length i from theconstraint length decision means with the aid of inverse conversiontables of inverse converting n×i bit variable length code into m×i bitdata.

With the first modulation method of the present invention, whenconverting data having the minimum run d of 4 or more and the basic datalength of m bits into the variable length code (d, k; m, n; r) havingthe basic code length of n bits, the bit at a preset position of acodeword which is likely to give an infinite number (∞) of the maximumrun k and the bit at a preset position of a codeword which gives themaximum number of "0"s consecutive from its least significant bittowards the upper order bit side is an unfixed bit the value of which isfixed depending on the number of "0"s consecutive thereto.

With the second modulation method according to the present invention,the unfixed bit is set to "1" when d or more bits are consecutive to theunfixed bit.

In this manner, the minimum length between transitions T_(min) may beincreased to 5T from 3T for EFM, thereby improving the recordingdensity. In addition, the distributions of the minimum length betweentransitions T_(min) may be concentrated in the vicinity of 5T. On theother hand, the maximum length between transitions T_(max) may bediminished to, for example, 19T, from 23T for VFM having the same valueof the minimum length between transitions T_(min), thereby simplifyingthe designing of the apparatus from the aspects of clock reproductionand jitter. In addition, the ratio of the maximum length betweentransitions to the minimum length between transitions may be reduced to3.8 from 4.6 for VFM.

With the demodulation apparatus according to the present invention, inwhich the variable length code (d, k: m, n; r) having a minimum run d of0.4 or more and the basic code length of n bits, and including acodeword having an unfixed bit the value of which is determined by thenumber of "0"s consecutive to the unfixed bit, is inverse converted intodata having a basic data length of m bits, the codeword braving theunfixed bit is detected, and the constraint length i of the variablelength code is determined based upon the results of detection. Thevariable length code is then inverse-converted into data, on the basisof the constraint length i, with the aid of inverse conversion tablesfor inverse conversion of the n×i bit variable length code into m×i bitdata. In this manner, the variable length code including variable lengthcodeword may be demodulated into data. In addition, the inverseconversion tables for inverse conversion of the variable length codeinto data and hence the circuit scale may be reduced in size as comparedto those of VFM, thereby decreasing the cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block circuit diagram showing a circuit arrangement for amodulating apparatus according to the present invention.

FIG. 2 is a graph showing the distribution of the transition lengthswith the modulating method according to the present invention ascompared to that with the conventional VFM.

FIG. 3 is a block diagram showing a concrete circuit arrangement of ademodulating apparatus according to the represent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to the drawings, preferred embodiments of the modulatingmethod and the demodulating apparatus according to the present inventionare explained in detail. In these embodiments, the present invention isapplied to a modulating apparatus for translating data into variablelength code (d, k; m, n; r) and a demodulating apparatus for performingan inverse operation of the above-mentioned translating operation.FIGS.1 and 3 illustrate circuit arrangements for the modulatingapparatus and the demodulating apparatus, respectively.

Referring to FIG. 1, the modulating apparatus includes a shift register11 for shifting data based on m bits as a unit, and an encoding circuit12 for discriminating the constraint length i (i=1 to r) of datasupplied from the shift register 11, based upon m bits as a unit, andfor detecting data which is to be transformed into a codeword includingan unfixed bit, referred to hereinafter as an unfixed codeword. Theapparatus also includes conversion tables aweigh, i being 1 to r, fortranslating data having a minimum run d of not less than four and abasic data length of m bits into a variable length code (d, k; m, n; r)having a basic codeword length of i bits, and a selector 13 forselecting one of the conversion tables 14₁ based upon the constraintlength i from the encoding circuit 12 for supplying m×i bit data to theconversion tables 14₁. The apparatus also includes an unfixed bitprocessing circuit 16₁ for setting a bit of a pre-set position of acodeword from the conversion table 14₁ which gives an infinite number(∞) of the maximum run k and a bit of a pre-set position of a codewordfrom the conversion table 14₁ having the maximum number of consecutive0's from the least significant bit towards the upper order bit side andfor setting the value of the unfixed bit to 1 when d or more bits areconsecutive to the unfixed bit, and a selector 15 for selecting one ofthe unfixed bit processing circuits 16₁ based upon the results ofdetection from the encoding circuit 12 and supplying the unfixed bit tothe selected one of the unfixed bit processing circuit 16_(i). Theapparatus also includes a multiplexor 17 for commutatively selecting thecodeword from the selector 15 or the codeword from the unfixed bitprocessing circuit 16₁ for outputting the selected codeword as serialdata, and a buffer memory 18 for temporarily storing the variable lengthcodeword from the multiplexor 17 and outputting the stored codeword asthe modulated codeword at a pre-set transfer rate. Finally, theapparatus includes a clock generator 19 for supplying clocks to thebuffer memory 18.

Now, assuming that the variable length code (d, k; m, n; r) is the code(4, 18; 2, 5; 6), with a minimum d run of not less than 4, a maximum runk of 0's equal to 18 bits, a basic data length m of 2 bits, a basiccodeword length n of 5 bits and with a maximum constraint length r of 6bits. Then, as shown in Table 2, the conversion table 14₁ is aconversion table for converting 2×1 bits or 2 bits, with the constraintlength i equal to 1, into the codeword having the length of 5×1 bits or5 bits, referred to hereinafter as a 2-5 conversion table. Theconversion table 14₂ is a conversion table for converting 4 bits, withthe constraint length i equal to 2, into a 10-bit codeword, referred tohereinafter as a 4-10-conversion table. In a similar manner, theconversion tables 14₃ to 14₆ are a 6-15 conversion table, a 8-20conversion table, 10-25 conversion table and a 12-30 conversion table,respectively.

In these conversion tables, some of the conversion tables have acodeword the maximum run k of which becomes equal to ∞ if the unfixedbit is set to 0. An example is the conversion table 14₁ (2-5 conversiontable) that has a coding rule for converting data "01" in binaryrepresentation into a codeword "00*00" in which a bit as from the leastsignificant bit (LSB) up to the m'th bit which, if set to 1, will givethe least value of the maximum length of transition T_(max), becomes anunfixed bit, where * is fixed to 1 or 0 depending on the number of 0'sconsecutive thereto. The conversion table 14₂ (4-10 conversion table)has a coding rule of converting data "1011" into a codeword "0000000*00". The conversion table including a codeword in which the number of0's consecutive from the LSB towards the upper order side becomesmaximum, such as the conversion table 14₄ (8-20 conversion table), has acoding rule of converting data "00000100" into a codeword "00000 0000000100 00*00". These conversion tables are implemented by, for example, aROM in which the values of the codewords are previously stored with thedata as addresses.

                  TABLE 2                                                         ______________________________________                                        data words        codewords                                                   ______________________________________                                        i=1  11           10000                                                            10           01000                                                            01           00*00                                                       i=2  0011         00010 00000                                                      0010         00001 00000                                                      1011         00000 00*00                                                 i=3  000111       00010 00010 00000                                                000110       00010 00001 00000                                                000101       00001 00001 00000                                                000100       00000 00010 00000                                                000011       00000 00001 00000                                           i=4  00001011     00010 00010 00010 00000                                          00001010     00010 00010 00001 00000                                          00001001     00010 00001 00001 00000                                          00001000     00001 00001 00001 00000                                          00000111     00000 00010 00010 00000                                          00000110     00000 00010 00001 00000                                          00000101     00000 00001 00001 00000                                          00000100     00000 00000 00100 00*00                                     i=5  0000001111   01000 00000 00000 00010 00000                                    0000001110   01000 00000 00000 00001 00000                                    0000001101   00100 00000 00000 00010 00000                                    0000001100   00100 00000 00000 00001 00000                                    0000001011   00010 00010 00010 00010 00000                                    0000001010   00010 00010 00010 00001 00000                                    0000001001   00010 00010 00001 00001 00000                                    0000001000   00010 00001 00001 00001 00000                                    0000000111   00001 00001 00001 00001 00000                                    0000000110   00000 00010 00010 00010 00000                                    0000000101   00000 00010 00010 00001 00000                                    0000000100   00000 00001 00001 00001 00000                                    0000000011   00000 00001 00001 00001 00000                                    0000000010   00000 00000 00100 00010 00000                                    0000000001   00000 00000 00100 00001 00000                               i=6  000000000011 00010 00010 00010 00010 00010 00000                              000000000010 00010 00010 00010 00010 00001 00000                              000000000001 00010 00010 00010 00001 00001 00000                              000000000000 00010 00010 00001 00001 00001 00000                         ______________________________________                                    

The shift register 11 is supplied with data obtained by processing videosignals with data compression operations, such as predictive coding,discrete cosine transform, Huffman coding or the like. The shiftregister 11 shifts the input data, based upon m bits as a unit, andoutputs the data to the encoding circuit 12.

The encoding circuit 12 discriminates the constraint length i of theinput data supplied thereto based upon m bits as a unit. Specifically,the encoding circuit 12 checks if data supplied thereto on the 2-bitbasis is presenting the data portion of the 2-5 conversion table shownin Table 2. That is, the encoding circuit determines the constraintlength i to be 1 when the data is "11", "10" and "01" and, if the datais "00", it adds the next two bits to produce 4 bits, that is it shiftsthe input data to the next rank. If data "10" and data "11" areconsecutive to each other in this order, the constraint length i isdetermined to be 2 in order to prevent the maximum run of the variablelength code produced on conversion from becoming infinite (∞).

The encoding circuit 12 checks if 4-bit data supplied thereto is presentin a data portion of the 4-10 conversion table shown in Table 2. Thatis, the encoding circuit determines the constraint length i to be 2 whenthe data is "0011", "0010"' and "1011" and, if the data is "0001" or"0000", it shifts the input data to the next rank.

In a similar manner, the encoding circuit 12 determines the dataportions of the 6-15 conversion table, 8-20 conversion table or the10-25 conversion table in which the data supplied on the 2-bit basisfrom the shift register 11 is present, and accordingly determines theconstraint length i=3 to 6.

The encoding circuit 12 also detects data "01", "1011" and "00000100"and detects these data as being data in which the codeword produced onconversion becomes an unfixed codeword.

The selector 13 then selects the conversion table 14i based upon theconstraint length i supplied from the encoding circuit 12, and routesm×i bit data to the thus selected conversion table 14i.

Specifically, the selector 13 selects the conversion table 14, when i=1and routes 2-bit data "11", "10" and "01" to the thus selectedconversion table 14_(i).

The selector 13 selects the conversion table 1₂ when i=2 and routes4-bit data "0011", "0010" and "1011" to the thus selected conversiontable 14₂. If the data "10" and data "11" are consecutive in this order,the selector selects the conversion table 14₂ and routes 4-bit data"1011" to the conversion table 14₂.

In a similar manner, the selector 13 selects the conversion tables 14₃to 14₆, associated with the value of the constraint length i, if theconstraint length i is 3 to 6, and routes 6-12 bit data to the thusselected conversion tables 14₃ to 14₆.

The conversion tables 14₁ to 14₆ have the 2-5, 4-10, 6-15, 8-20, 10-25and 12-30 conversion tables, as explained hereinabove, and reads out thecodewords of the codeword portion, using the data supplied via theselector 13 as the readout addresses.

The result is that if the data is "11", "10" and "01", the conversiontable 14₁, outputs the codewords "10000", "01000" and an unfixedcodeword "00*00", respectively

If the data is "0011", "0010" and "1011", the conversion table 14₂outputs the codewords "00010 00000", "00001 00000" and an unfixedcodeword "00000 00*00", respectively.

If the data is "000111", "000110", "000011", the conversion table 14₃outputs the codewords "00010 00010 00000", "00010 00001 00000",'. -"00000 00001 00000".

If the data is "00001011", "00001010 00000100", the conversion table 14₄outputs the codewords "00010 00010 00010 00000", "00010 00010 0000100000" and an unfixed codeword "00000 00000 00100 00*00", respectively.

If the data is "0000001111", "0000001110 0000000001" the conversiontable 14₅ outputs the codewords "01000 00000 00000 00010 00000", "0100000000 00000 00001 00000", "00000 00000 00100 00001 00000", respectively.

If the data is "000000000011" "000000000010". . . "000000000000", theconversion table 14₆ outputs the codewords "00010 00010 00010 0001000010 00000", "00010 00010 00010 00010 00001 00000". . . "00010 0001000001 00001 00001 00000", respectively.

That is, these conversion tables 14₁ to 14₆ output variable lengthcodewords and route these codewords to the selector 15. The selector 15selects the unfixed bit processing circuit 16j_(i), based upon theresults of detection of the unfixed codeword, supplied from the encodingcircuit 12, and routes the unfixed codeword to the unfixed bitprocessing circuit 16_(j), while routing the codewords other than theunfixed codeword to the multiplexor 17.

Specifically, the selector 15 selects, when supplied with an unfixedcodeword "00*00" containing the unfixed bit "*", the unfixed bitprocessing circuit 16₁ based upon the results of detection of theunfixed codeword, and routes the unfixed codeword "00*00" to the unfixedbit processing circuit 16_(j)

When supplied with the unfixed codeword "00000 00*00", for example, theselector 15 selects the unfixed bit processing circuit 16₂, and routesthe unfixed codeword "00000 00*00" to the unfixed bit processing circuit16₂.

When supplied with the unfixed codeword "00000 00000 00100 00*00", forexample, the selector 15 selects the unfixed bit processing circuit 16₄,and routes the unfixed codeword "00000 00000 00100 00*00" to the unfixedbit processing circuit 16₄.

The unfixed bit processing circuit 16, sets the unfixed bit of theunfixed codeword "00*00", that is the third bit as counted from the LSBbeing the first bit, to 1 when not less than d "0" bits are continuouslyadjacent to the unfixed bit. Specifically, if the unfixed codeword"00*00" is followed by the codeword "10000", the processing circuit16_(i), sets the unfixed codeword "00*00" fixedly to a codeword "00000".On the other hand, if the codeword "00010 00000" is followed by theunfixed codeword "00*00", the unfixed codeword is set fixedly to acodeword 00100.

Also the unfixed bit processing circuit 16₂ sets the unfixed codeword"00000 00*00" fixedly to a codeword "00000 00100" or to a codeword"00000 00000" depending on the number of "0"s consecutive to the unfixedbit.

Furthermore, the unfixed bit processing circuit 16₄ sets the unfixedcodeword "00000 00000 00100 00*00" fixedly to a codeword "00000 0000000100 00100" or to a codeword "00000 00000 00100 00000" depending on thenumber of "0"s consecutive to the unfixed bit.

The multiplexor 17 multiplexes the codeword from the selector 15 and thecodeword fixed by the unfixed bit processing circuit 16_(j) to produceserial data which is supplied to the buffer memory 18.

The buffer memory 18 transiently stores the codewords supplied theretofrom the multiplexor 17 and outputs the stored codewords as thecodewords at a pre-set transfer rate in relation to the clocks suppliedfrom the clock generator 19.

That is, if the bit length of the NRZI modulated variable lengthcodeword, referred to herein as the recording waveform data string, isT, the minimum length between transitions T_(min) with the variablelength code (4, 18; 2, 5; 6) of the present embodiment is (4+1)T or 5T.The maximum length between transitions T_(max) is (18+1)T or 19T, whilethe window margin T_(W), which gives an allowable jitter valuerepresented by (m/n)×T, has a value equal to 2/5T or 0.4T. The ratio ofthe maximum length between transitions to the minimum length betweentransitions, as referred to in connection with the prior art, is 3.8(T_(max) /T_(min) =19T/5T).

In other words, with the present variable length code (4, 18; 2, 5; 6),the minimum length between transitions T_(min) may be increased to 5Tfrom the minimum length between transitions T_(min) of the eight tofourteen modulation (EFM), that is the variable length code (2, 10; 8,17; 1), which is 3T, thus improving the recording density. In addition,the distribution of the minimum length between transitions T_(min) maybe concentrated in the vicinity of 5T, as shown for example in Table 3and FIG.2. Specifically, as shown in FIG. 2, the occurrences of 5T and6T may be increased by approximately 17% and 14%, respectively, ascompared to those in the case of variable five modulation (VFM). Thatis, for a variable length code (4, 22; 2, 5; 5) referred to inconnection with the prior art, the mean length between transitions,which is the total number of bits divided by the number of times oftransitions, may be decreased to 7.82 from 8.21 for VFM.

                  TABLE 3                                                         ______________________________________                                        length between                                                                transitions VFM       (4,18; 215; 6)                                                                           (4,19; 2,5; 5)                               ______________________________________                                         5T         423       505        495                                           6T         336       383        378                                           7T         292       312        314                                           8T         242       238        236                                           9T         147       152        154                                          10T         132       125        126                                          11T         102       106        107                                          12T         82        66         68                                           13T         61        63         63                                           14T         44        51         49                                           15T         23        32         32                                           16T         23        20         22                                           17T         21        17         is                                           18T         20        6          9                                            19T         12        2          2                                            20T         10                   1                                            21T         4                                                                 22T         2                                                                 23T         0                                                                 number of times                                                                           1985      2078       2071                                         of transition                                                                 number of bits                                                                            16300     16255      16280                                        mean length 8.21      7.82       7.86                                         between                                                                       transitions                                                                   ______________________________________                                    

In addition, with the present variable length code (4, 18; 2, 5; 6), themaximum length between transitions T_(max) may be diminished to 19T, ascompared to the maximum length between transitions T_(max) equal to 23Tfor VFM having the same value for the minimum length between transitionsT_(min). The design of the apparatus is thereby simplified from thestandpoint of clock reproduction and jitter. Further, the ratio of themaximum length between transitions to the minimum length betweentransitions may be diminished to 3.8 as compared to the value of thesame ratio of 4.6 for VFM.

Also, as may be seen from tables 1 and 2, the conversion tables 14₁ to14₆ of the variable length code (4, 18; 2, 5; 6) may be rendered smallerthan those for VFM.

It is also noted that, if the bit length of the data string is T₁, theminimum length between transitions T_(1min) and the maximum lengthbetween transitions T_(1max), based on the bit length T₁, as areference, are 2.0T₁, and 7.6T₁, respectively.

The modulation method according to the present invention is not limitedto the above-described embodiment. For example, the variable length codemay also be a variable length code (4, 19; 2, 5; 5) which is inclusiveof unfixed bits such as those in unfixed codewords "00*00", "0000000*00", "00000 00000 00100 00*00" and "00000 00000 00010 000*0" andwhich is made up of a 2-5 , 4-10. 6-15, 8-20 and 10-25 conversiontables. In this case, the minimum length between transitions T_(min),the maximum length between transitions T_(max), window margin T_(W) andthe ratio of the maximum length between transitions to the minimumlength between transitions are equal to 5T (2.0T_(i), 20T (8.0T₁,), 0.4and 4.0, respectively, such that the maximum length between transitionsT_(max) and the ratio of T_(max) to T_(min) may be smaller than thosefor VFM.

Table 4 shows another example of the conversion tables, which may beemployed in the modulation method according to the present invention.

                  TABLE 4                                                         ______________________________________                                        data words        codewords                                                   ______________________________________                                        i=1  11           10000                                                            10           01000                                                            01           00*00                                                       i=2  0011         00010 00000                                                      0010         00001 00000                                                      1011         00000 00*00                                                 i=3  000111       00010 00010 00000                                                000110       00010 00001 00000                                                000101       00001 00001 00000                                                000100       00000 00010 00000                                                000011       00000 00001 00000                                           i=4  00001011     00010 00010 00010 00000                                          00001010     00010 00010 00001 00000                                          00001001     00010 00001 00001 00000                                          00001000     00001 00001 00001 00000                                          00000111     00000 00010 00010 00000                                          00000110     00000 00010 00001 00000                                          00000101     00000 00001 00001 00000                                          00000100     00000 00000 00100 00*00                                          00000011     00000 00000 00010 000*0                                     i=5  0000001011   00010 00010 00010 00010 00000                                    0000001010   00010 00010 00010 00001 00000                                    0000001001   00010 00010 00001 00001 00000                                    0000001000   00010 00001 00001 00001 00000                                    0000000111   00001 00001 00001 00001 00000                                    0000000110   00000 00010 00010 00010 00000                                    0000000101   00000 00010 00001 00001 00000                                    0000000000   00000 00010 00001 00001 00000                                    0000000011   00000 00001 00001 00001 00000                                    0000000010   00000 00000 00100 00010 00000                                    0000000001   00000 00000 00100 00001 00000                                    0000000000   00000 00000 00010 00001 00000                               ______________________________________                                    

The other embodiments of the conversion tables applicable for themodulation method according to the present invention are hereinafterexplained.

Table 5 also shows a conversion table of the variable length code (4,18; 2, 5; 5), which represents an example in which the size is reducedby employing a large number of unfixed bits *.

                  TABLE 5                                                         ______________________________________                                        data words        codewords                                                   ______________________________________                                        i=1  11           10000                                                            10           01000                                                            01           00*00                                                       i=2  0011         00010 00000                                                      0010         00001 00000                                                      1011         00000 00*00                                                 i=3  000111       00010 00010 00000                                                000110       00010 00001 00000                                                000101       00001 00001 00000                                                000100       00000 00010 00000                                                000011       00000 00001 00000                                           i=4  00001011     00010 00010 00010 00000                                          00001010     00010 00010 00001 00000                                          00001001     00010 00001 00001 00000                                          00001000     00001 00001 00001 00000                                          00000111     00000 00010 00010 00000                                          00000110     00000 00010 00001 00000                                          00000101     00000 00001 00001 00000                                          00000100     00000 00000 00100 0000*                                     i=5  0000001111   00010 00010 00010 00010 00000                                    0000001110   00010 00010 00010 00001 00000                                    0000001101   00010 00010 00001 00001 00000                                    0000001100   00010 00001 00001 00001 00000                                    0000001011   00001 00001 00001 00001 00000                                    0000001010   00000 00010 00010 00010 00000                                    0000001001   00000 00010 00010 00001 00000                                    0000001000   00000 00010 00001 00001 00000                                    0000000111   00000 00000 00100 00100 0000*                                    0000000110   00000 00000 00100 00010 00000                                    0000000101   10000 00000 00000 00010 00000                                    0000000100   10000 00000 00000 00001 00000                                    0000000011   01000 00000 00000 00010 00000                                    0000000010   01000 00000 00000 00001 00000                                    0000000001   00100 00000 00000 00010 00000                                    0000000000   00100 00000 00000 00001 00000                               ______________________________________                                    

Table 6 shows a conversion table for the variable length code (4, 19; 2,5; 6). Although the size is enlarged as compared to those shown intables 2 and 4, the number of unfixed bits * is diminished to avoidcomplexity of operation in order to achieve a more favorable hardwareconfiguration

                  TABLE 6a                                                        ______________________________________                                        data words        codewords                                                   ______________________________________                                        i=1  11           10000                                                            10           01000                                                            01           000*0                                                       i=2  0111         00100 00000                                                      0010         00001 00000                                                      1011         00000 000*0                                                 i=3  000111       00100 00100 00000                                                000110       00100 00010 00000                                                000101       00100 00001 00000                                                000100       00001 00001 00000                                                000011       00000 00001 00000                                           i=4  00001011     00100 00100 00100 00000                                          00001010     00100 00100 00010 00000                                          00001001     00100 00100 00001 00000                                          00001000     00100 00010 00000 00000                                          00000111     00100 00010 00001 00000                                          00000110     00100 00001 00001 00000                                          00000101     00001 00001 00001 00000                                          00000100     00000 00001 00001 00000                                     ______________________________________                                    

                  TABLE 6b                                                        ______________________________________                                        data words        codewords                                                   ______________________________________                                        i=5  0000001111   00100 00100 00100 00100 00000                                    0000001110   00100 00100 00100 00010 00000                                    0000001101   00100 00100 00100 00001 00000                                    0000001100   00100 00100 00010 00010 00000                                    0000001011   00100 00100 00010 00001 00000                                    0000001010   00100 00100 00001 00001 00000                                    0000001001   00100 00010 00010 00010 00000                                    0000001000   00100 00010 00001 00001 00000                                    0000000111   00100 00010 00001 00001 00000                                    0000000110   00100 00001 00001 00001 00000                                    0000000101   00001 00001 00001 00001 00000                                    0000000100   00000 00001 00001 00001 00000                               i=6  000000001111 00100 00100 00100 00100 00100 00000                              000000001110 00100 00100 00100 00100 00010 00000                              000000001101 00100 00100 00100 00100 00001 00000                              000000001100 00100 00100 00100 00010 00010 00000                              000000001011 00100 00100 00100 00010 00001 00000                              000000001010 00100 00100 00100 00001 00001 00000                              000000001001 00100 00100 00010 00010 00010 00000                              000000001000 00100 00100 00010 00010 00001 00000                              000000000111 00100 00100 00010 00001 00001 00000                              000000000110 00100 00100 00001 00001 00001 00000                              000000000101 00100 00010 00010 00010 00010 00000                              000000000100 00100 00010 00010 00010 00001 00000                              000000000011 00100 00010 00010 00001 00001 00000                              000000000010 00100 00010 00001 00001 00001 00000                              000000000001 00100 00001 00001 00001 00001 00000                              000000000000 00001 00001 00001 00001 00001 00000                         ______________________________________                                    

Table 7 shows a conversion table for the variable length code (4, 20; 2,5; 5). Although T_(max) becomes larger than that with the other codes,the size may be reduced.

                  TABLE 7                                                         ______________________________________                                        data words        codewords                                                   ______________________________________                                        i=1  11           10000                                                            10           01000                                                            01           0000*                                                       i=2  0011         00100 00000                                                      0010         00010 00000                                                      1011         00000 0000*                                                 i=3  000111       00100 00100 00000                                                000110       00100 00010 00000                                                000101       00100 00001 00000                                                000100       00010 00010 00000                                                000011       00010 00001 00000                                           i=4  00001011     00100 00100 00100 00000                                          00001010     00100 00100 00010 00000                                          00001001     00100 00100 00001 00000                                          00001000     00100 00010 00010 00000                                          00000111     00100 00010 00001 00000                                          00000110     00100 00010 00010 00000                                          00000101     00100 00010 00001 00000                                          00000100     00010 00010 00010 00000                                          00000011     00010 00010 00001 00000                                          00000010     00010 00001 00001 00000                                     i=5  0000000111   00100 00100 00100 00100 00000                                    0000000110   00100 00100 00100 00010 00000                                    0000000101   00100 00100 00100 00001 00000                                    0000000100   00100 00100 00010 00010 00000                                    0000000011   00100 00100 00010 00001 00000                                    0000000010   00100 00100 00001 00001 00000                                    0000000001   00100 00010 00010 00010 00000                                    0000000000   00100 00010 00010 00001 00000                               ______________________________________                                    

The modulation apparatus is hereinafter explained.

The present demodulation apparatus includes an unfixed codewarddetection circuit 21 for detecting a codeword including an unfixed bitfrom the variable length code (d, k; m, n; r) having a minimum run d of4 and a basic codeword length of n bits, with the unfixed bit being at apre set position as determined by the number of "0"s consecutive to thepreset bit position, and constraint length determining circuits 22a,22b, for determining the constraint length i of the variable length codebased upon the results of detection by the unfixed codeword detectioncircuit 21. The apparatus also includes inverse conversion tables24a_(i), 24b₁ for inverse conversion of the n×i bits of the variablelength code into m×i data, where i=1 to r, and selectors 23a, 23b forselecting the inverse conversion tables 24a_(i), 24b₁ based upon theconstraint length i from the constraint length determining circuits 22a,22b and supplying the n×i bit variable length codewords to the selectedinverse conversion tables 24ai, 24b_(i). The apparatus also includesmultiplexors 25a, 25b for commutatively selecting data from the inverseconversion tables 24a_(i), 24b₁ and outputting the selected data asserial data, and a buffer memory 26 for transiently storing data fromthe multiplexors 25a and 25b and outputting the stored data as playbackdata. Finally, the apparatus includes a phase locked loop (PLL) 27 forreproducing clocks based upon the variable length code and supplying theclocks to the buffer memory 26.

Assuming that the variable length code (d, k; m, n; r) is the variablelength code (4, 19; 2, 5; 5) in which the minimum run d is 4 bits, themaximum run k is 19 bits, the basic data length m is 2 bits, the basiccodeword length n is 5 bits and the maximum constraint length r is 5,the inverse conversion tables 24a₁, 24b₁, on the whole are inverseconversion tables corresponding to the 2-5 conversion tables shown intable 4, i.e., is inverse conversion tables each having a constraintlength i equal to 1 and adapted for converting a 5-bit codeword into2-bit data, referred to hereinafter as 5-2 conversion tables. Of theseinverse conversion tables, the inverse conversion table 24a₁, is forcodewords liable to unfixed codewords, that is codewords in which fivebits as counted from the MSB are "00000" or "00100", whereas the inverseconversion table 24b₁ for other codewords, that is codewords in whichfive bits as counted from the MSB are "10000" or "01000".

On the other hand, the inverse conversion tables 24a₂, 24b₂ on the wholeare inverse conversion tables corresponding to the 4-10 conversiontables shown in table 4, that is inverse conversion tables each having aconstraint length i equal to 2 and adapted for converting a 10-bitcodeword into 4-bit data, referred to hereinafter as 10-4 inverseconversion tables. Of these inverse conversion tables, the inverseconversion table 24a₂ is for codewords liable to unfixed codewords, thatis a codeword in which five bits as counted from the MSB are "00000","00001" whereas the inverse conversion, tables 24b₂ is for othercodewords, that is codewords in which five bits as counted from the MSBare "00010, "00001".

In a similar manner, the inverse conversion tables 24a₃ and 24b₃comprise 15-6 inverse conversion tables having a constraint length iequal to 3 and adapted for converting 15-bit codewords into 6-bit data,while the inverse conversion tables 24a₄, 24b₄ comprise 20-8 inverseconversion tables having a constraint length i equal to 4 and adaptedfor converting 20-bit codewords into 8-bit data, and the inverseconversion tables 24a₅, 24b₅ comprise 25-10 inverse conversion tableshaving a constraint length i equal to 5 and adapted for converting25-bit codewords into 10-bit data.

Referring to FIG. 3, the unfixed-bit detection circuit 21 is made up ofan unfixed pattern detection circuit 21a for detecting a 5-bit patternincluding an unfixed bit, referred to hereinafter as an unfixed pattern,and an unfixed codeword decision circuit 21b for detecting the unfixedcodeword based upon the results of detection from the unfixed patterndetection circuit 21a, These circuits are fed with variable lengthcodewords corresponding to the data reproduced from the recording mediumand subsequently processed with NRZI demodulation, error correction orthe like.

The unfixed pattern detection circuit 21a detects the unfixed patternsbased upon a group of 5 bits from the leading end as a unit ofdetection. Specifically, there are two patterns likely to unfixedpatterns, that is patterns "00000" and "00100". The detection circuit21a detects these patterns "00000" and "00100" and routes the results ofdetection to the unfixed codeword discrimination circuit 21b.

When the unfixed codeword discrimination circuit 21b detects the pattern"00100", it determines the pattern to be an unfixed codeword "00*00".When the discrimination circuit detects the pattern "00000", it combinesthe pattern with the next 5-bit pattern to produce a 10-bit pattern andchecks if the 10-bit pattern corresponds to patterns "00000 10000","00000 01000" or "00000 00100". If the 10-bit pattern corresponds to thepatterns "00000 10000" or "00000 01000', the discrimination circuitdetermines the first 5-bit pattern "00000" to be an unfixed codeword"00*00". If the 10-bit pattern corresponds to the pattern "00000 00100",the discrimination circuit determines the 10-bit pattern "00000 00100"to be an unfixed codeword "00000 00*00".

In a similar manner, the discrimination circuit 21b detects unfixedcodewords, such as "00000 00000 00100 00*00" or "00000 00000 00010000*0" as it appends 5 bits each time, and routes the results ofdetection of the unfixed codeword to the constraint length decisioncircuits 22a, 22b.

Based upon the results of detection of the unfixed codewords, suppliedfrom the unfixed codeword discrimination circuit 21b, the constraintlength discrimination circuits 22a and 22b determine the constraintlength i of the unfixed codeword and the constraint length i of thecodewords other than the unfixed codewords, respectively.

Based upon the constraint length i from the constraint lengthdiscrimination circuits 22a, 22b, the selectors 23a, 23b select theinverse conversion tables 24a_(i), 24b₁ and routes n×i bit variablelength codewords to the thus selected inverse conversion tables 24a_(i),24b.

Specifically, when i=1, for example, the selector 23a selects theinverse conversion table 24a₁ and routes 5-bit codewords 00000" or"00100" to the thus selected inverse conversion table 24a₁, while theselector 23b selector the inverse conversion table 24b₁ and routes 5-bitcodewords "10000" or "01000" to the thus selected inverse conversiontable 24b₁.

On the other hand, when i=2, for example, the selector 23a selects theinverse conversion table 24a and routes 10-bit codewords "00000 00000"or "00000 00100" to the thus selected inverse conversion table 24a₂,while the selector 23b selects the inverse conversion table 24b₂ androutes 10-bit codewords "00010 00000" or "'00001 00000" to the thusselected inverse conversion table 24b₂.

In a similar manner, when the constraint length i is 3 to 5, theselectors 23a, 23b select the inverse conversion tables 24a₃ to 24a₅ and24b₃ to 24b₅ and routes 15 to 25 bit codewords to the selected inverseconversion tables 24a₃ to 24a₅ and 24b₅.

The inverse conversion tables 24a₁ to 24a₅ and 24b₁ to 24b₅ each have a5-2, 10-4, 15-6, 20-8 and 25-10 inverse conversion, tables, and read outdata of the data portions shown in table 4, using the codewords from theselectors 23a and 23b as the readout addresses.

The result is that, for the codewords "10000", "01000" and "00*00", theinverse conversion table 24b, outputs data "11" and "10" respectively,while the inverse conversion table 24a₂ outputs data "1011".

For the codewords "00010 00000", "00001 00000" and "00000 00*00", theinverse conversion table 24b₂ outputs data "0011" and "0010", while theinverse conversion "table 24a₂ outputs data "1011".

For the codewords "00010 00010 00010 00000", "00010 00001 00000", "0000000001 00000", the inverse conversion table 24b₅ outputs data "000111","0001010", "00011".

For the codewords "00010 00010 00010 00000", "00010 00010 00001 00000","00000 00000 00010 00*00", the inverse conversion table 24b₄ outputsdata "00001011", "00001010", - "00000101", while the inverse conversiontable 24b₄ outputs data "00000100" and "00000011".

For the codewords "00010 00010 00010 00010 00000", "00010 00010 0001000001 00000, "00000 00000 00010 00001 00000", the inverse conversiontable 24b₅ outputs data "0000001101", "0000001010", "0000000000.

That is, 2×i bit data, as inverse converted from 5×i bit variable lengthcodewords, are outputted from these inverse conversion tables 24a₁, to24a₅ and 24b₁, to 24b₅ and routed to the multiplexors 25a and 25b.

The multiplexors 25a and 25b multiplex the data routed from the inverseconversion tables 24a₁, to 24a₅ and 24b₁, to 24b₅ and transmit theresulting data as serial data to the buffer memory 26.

On the other hand, the PLL 27 reproduces clocks based upon the variablelength codewords, and transmits the reproduced clocks to the buffermemory 26.

The buffer memory 26 temporarily stores data supplied thereto from themultiplexors 25a, 25b and outputs the stored data at a preset rate asplayback data in a timed relation to the clocks supplied thereto fromthe PLL 27. These output data are processed, for example, with inverseDCT, predictive decoding or the like, for reproducing video signals.

With the present demodulation apparatus, the variable length codeincluding an unfixed codeword into data may be demodulated by detectingthe codeword having the unfixed bit, determining the constraint length iof the codeword of the variable length code based upon the results ofdetection, and inverse-converting the codeword into data based upon theconstraint length i with the aid of the inverse conversion tables forinverse converting the n×i bit variable length code into m×i bit data.With the present demodulating apparatus, similarly to the modulationapparatus, the inverse conversion tables 24a₁ to 24b₅ and 24b₁ tl 255and hence the circuit size may be reduced as compared to that of theVFM. In addition, since the maximum length between transitions T_(max)may be diminished as compared to that of VFM, the PLL 27 may be improvedin reliability.

What is claimed is:
 1. A modulation method for converting data having aminimum run of 4 or more and a basic data length of m bits into avariable length code (d, k; m, n; r) having a basic code length of nbits, comprisingsetting an unfixed bit located at a preset position of acodeword that is capable of producing a maximum run k that is infinite,and determining said unfixed bit depending upon a codeword consecutiveto said unfixed bit.
 2. The modulation method as claimed in claim 1comprising setting the unfixed bit to "1" when d or more bits areconsecutive to said unfixed bit.
 3. A modulation method for convertingdata having a minimum run of 4 or more and a basic data length of m bitsinto a variable length code (d, k; m, n; r) having a basic code lengthof n bits, comprisingsetting a bit at a preset position of a codewordwhich has the maximum number of "0"s consecutive thereto from its leastsignificant bit towards the upper order bit side as an unfixed bit, anddetermining said unfixed bit depending upon a codeword consecutive tosaid unfixed bit.
 4. A modulation apparatus for converting digital datahaving the basic data length equal to m bits into a variable length code(d, k; m, n; r) having the basic codeword length of n bits,comprisingmeans for determining the constraint length i of said digitaldata, storage means in which conversion tables for converting saiddigital data into codewords of said variable length code having aminimum length between transitions T_(min) of 2.0 T or longer and aminimum length d of the same consecutive symbols of 4 or more, T beingthe bit length of said digital data, are stored, and in which a bit at apreset position of a codeword among said codewords likely to give amaximum run k is previously set as being an unfixed bit, modulationmeans for converting said digital data into said variable lengthcodewords, based upon the results of determination by said determiningmeans, with the aid of said conversion tables, and unfixed bitprocessing means for determining said unfixed bit depending upon thenext consecutive codewords if said unfixed bit is contained in thecodeword produced by said modulation means.
 5. The modulation apparatusas claimed in claim 4 whereinsaid storage means further sets a bit at apreset position of a codeword among the codewords in said conversiontable which has the maximum number of "0"s consecutive thereto from itsleast significant bit towards the upper order bit side as being anunfixed bit.
 6. The modulation apparatus as claimed in claim 5whereinsaid unfixed bit is present between the least significant bit andthe m'th bit of the variable length codeword and is such a bit as givesthe least value of the maximum length between transitions T_(max) if thebit is set to "1".
 7. The modulation apparatus as claimed in claim 6whereinsaid basic data length m is 2, the basic codeword length n is 5and the maximum constraint length r is 5 or
 10. 8. The modulationapparatus as claimed in claim 7 whereinif, for said maximum constraintlength r equal to 6, said maximum length between transitions T_(max) insaid variable length code is 7.6 T, T being the bit length of saiddigital data.
 9. The modulation apparatus as claimed in claim 7whereinif, for said maximum constraint length r equal to 5, said maximumlength between transitions T_(max) in said variable length code is 8.0T, T being the bit length of said digital data.
 10. The modulationapparatus as claimed in claim 4 whereinsaid constraint lengthdetermining means determines the constraint length based upon a locationwithin the conversion tables where a matching entry is found for theinputted digital data.
 11. The modulation apparatus as claimed in claim4 whereinsaid unfixed bit processing means determine said unfixed bit asbeing "1" when d or more "0" bits are consecutive to said unfixed bit.12. A modulation apparatus for converting a variable length code (d, k;m, n; r) having the basic codeword length of n bits into digital datahaving the basic data length equal to m bits, comprisinginverseconversion table storage means for storing inversion conversion tablesinverse-converting said variable length codewords into said digitaldata, said variable length codewords including such codeword in whichthe minimum length between transitions T_(min) is 2.0 T or longer, theminimum run d is 4 or longer and a bit at a preset position of thecodeword likely to give the maximum run k equal to ∞ is set as being anunfixed bit, T being a bit length of the digital data, unfixed bitdetection means for monitoring a string of said variable lengthcodewords on the n-bit basis and for detecting whether or not a presetcode pattern likely to have said unfixed bit is present in said string,unfixed bit determining means for determining, in accordance with theresults of detection by said unfixed pattern detection means, to whichcode portion of said inverse conversion table corresponds a codewordhaving said unfixed bit, constraint length determining means formonitoring the string of said variable length codewords for determiningthe constraint length of said variable length code, and demodulatingmeans for inverse converting said codewords into said digital data,based upon the results of decision of said unfixed codeword determiningmeans and said constraint length determining means, with the aid of saidinverse conversion tables, and outputting a resulting string of digitaldata.
 13. The demodulation apparatus as claimed in claim 12 whereinsaidinverse conversion table storage means set a bit at a preset position ofa codeword among the codewords in said inverse conversion tables whichgives a maximum number of consecutive "0"s from the least significantbit towards the upper order bit side thereof.
 14. The demodulationapparatus as claimed in claim 12 whereinsaid unfixed bit is positionedbetween the least significant bit and the m'th bit of the variablelength codeword.
 15. The demodulation apparatus as claimed in claim 14whereinsaid basic data length m is 2, the basic codeword length n is 5and the maximum constraint length r is 5 or
 6. 16. The demodulationapparatus as claimed in claim 14 whereinif, for said maximum constraintlength r equal to 6, said maximum length between transitions T_(max) insaid variable length code is 7.6 T, T being the bit length of saiddigital data.
 17. The demodulation apparatus as claimed in claim 14whereinif, for said maximum constraint length r equal to 5, said maximumlength between transitions T_(max) in said variable length code is 8.0T, T being the bit length of said digital data.